A magnetic random access memory (MRAM) is a non-volatile memory device using a magnetoresistance effect to store information. When using the magnetoresistance effect, the resistance of an electrically conductive material is changed using a circumferential magnetic field. An MRAM device may include a plurality of MRAM cells, with each cell having a magnetic tunnel junction (MTJ) and a single transistor.
An MTJ includes multiple thin layers such that electrons may tunnel through a very thin insulating layer sandwiched between two ferromagnetic electrodes when an external electrical signal is applied thereto. A top electrode of the two electrodes is called a free layer, and a bottom electrode is called a pinned layer.
When magnetization directions within the free layer and the pinned layer are arranged parallel with respect to each other, a tunneling current flowing through the MTJ may have a relatively high value. That is, the tunneling resistance may be relatively low. In contrast, when the magnetization directions within the free layer and the pinned layer are arranged anti-parallel with respect to each other, a tunneling current flowing through the MTJ may have a relatively low value. That is, the tunneling resistance may be relatively high.
An MRAM uses magnetization to store information while a conventional memory may use electrical charge. That is, digital data represented as ‘0’ and ‘1’ may be stored differently based on the low resistance state where the magnetization directions of the two electrodes are parallel with respect to each other and the high resistance state where the magnetization directions are anti-parallel with respect to each other.
An anti-ferromagnetic layer (which is referred to as a pinning layer) may be provided adjacent to the pinned layer. The pinning layer may fix the magnetization direction of the pinned layer. That is, the pinned layer adjacent to the pinning layer may have a relatively large switching field, and the magnetization direction of the pinned layer may be fixed in a constant direction when an applied magnetic field is less than the switching field. Thus, data of the MRAM cell may be determined as a function of the magnetization direction within the free layer. The magnetization direction of the free layer may be changed by applying a magnetic field to its circumference or perimeter. To change the magnetization direction of the free layer to a desired direction, conductive layers such as a bit line and a digit line may be formed orthogonal with respect to each other above and below the MTJ. Current may flow through each conductive layer so that a magnetic field generated therefrom may be used to change the magnetization direction of the free layer.
Most MTJs have a rectangular or elliptical shape when seen from a plan view so that magnetic spins within the free layer are in a stable state when they are parallel to the longitudinal direction of the free layer.
An integrated circuit MRAM device may include a plurality of MTJs. The MTJs may have non-uniform switching characteristics depending on a fabrication process used. In this case, external magnetic fields used to store desired data within different MTJs may be different. Accordingly, non-uniform switching characteristics of different MTJs may reduce a write margin for an MRAM device. In particular, when sizes of MTJs are reduced to increase integration density, a write margin may be significantly reduced. In other words, during a write operation to selectively store desired data in one of the MTJs, undesired data may be written in non-selected MTJs that share a bit line and/or a digit line shared with the selected MTJ. That is, according to conventional writing methods, a write disturbance may occur such that undesired data may be stored in non-selected MTJs during an operation to store data in the selected MTJ.
Furthermore, a conventional MRAM cell may have a digit line formed adjacent an MTJ as described above. In general, the digit line may be formed below the MTJ, and the MTJ may have a bottom electrode overlapping the digit line. In this case, the bottom electrode may be electrically connected to a drain region of an access transistor below the digit line. Thus, the bottom electrode may extend in a horizontal direction (parallel with respect to a surface of the substrate) to be in contact with a contact plug on the drain region. Accordingly, reducing an area of the MRAM cell may be difficult due to the presence of the digit line.
MRAM devices have been proposed which are suitable for application of a spin injection mechanism to reduce write disturbance and to increase integration density. For example, MRAM devices using the spin injection mechanism are discussed in U.S. Pat. No. 6,130,814 entitled “Current-Induced Magnetic Switching Device And Memory Including The Same” to Sun. Other MRAM devices using the spin injection mechanism are discussed in U.S. Pat. No. 6,603,677 entitled “Three-Layered Stacked Magnetic Spin Polarization Device With Memory” to Redon et al. The disclosures of U.S. Pat. Nos. 6,130,814 and 6,603,677 are hereby incorporated herein in their entirety by reference.
To switch a selected MRAM cell using the spin injection mechanism, the write current density may be greater than a critical current density. In this case, the access transistor should have the current drivability sufficient to generate a write current greater than the critical current density. That is, when the selected MRAM cell is programmed using the spin injection mechanism, it may be difficult to scale down the access transistors.
An MRAM device capable of extending a write margin by heating the MTJ is discussed in U.S. Pat. No. 6,603,678 B2 entitled “Thermally-Assisted Switching of Magnetic Memory Elements” to Nickel et al. the disclosure of which is hereby incorporated herein in its entirety by reference The MRAM device according to Nickel et al. has a plurality of parallel word lines, a plurality of parallel bit lines crossing above the word lines, a plurality of MTJ cells interposed between the word lines and the bit lines, and heating interconnections diagonally formed above the bit lines. The heating interconnections are formed of metal layers which are electrically insulated from the bit lines.